Latest revision as of 17:03, 3 February 2021

Abstract

Computer architectures used in safety-critical domains are subjected to worst-case execution time analysis. The presence of performance-driven microarchitectures may trigger undesired timing phenomena, called timing anomalies, and complicate the timing analysis. This paper investigates pipelines specifically designed to simplify the worst-case execution time analysis (also called predictable pipelines). We propose formal and executable models of four research-oriented pipelines and one industrial pipeline to validate some of their claims related to their timing behavior. We indeed validate, via bounded model checking, the absence of a type of timing anomalies called amplification timing anomalies, or its potential presence by identifying prerequisite to situations where they can occur.<br

Original document

The different versions of the original document can be found in:

• https://backend.orbit.dtu.dk/ws/files/199809995/verifypat.pdf

• http://xplorestaging.ieee.org/ielx7/9036752/9045099/09045351.pdf?arnumber=9045351,

http://dx.doi.org/10.1109/asp-dac47756.2020.9045351

• https://dblp.uni-trier.de/db/conf/aspdac/aspdac2020.html#JanASL20,

https://backend.orbit.dtu.dk/ws/files/199809995/verifypat.pdf,

https://orbit.dtu.dk/en/publications/formal-semantics-of-predictable-pipelines-a-comparative-study,

https://staging.orbit.dtic.dk/en/publications/formal-semantics-of-predictable-pipelines-a-comparative-study,

https://academic.microsoft.com/#/detail/3013903002

• https://orbit.dtu.dk/en/publications/ea3d0d25-efff-47f0-a04a-525703b6153a,

https://doi.org/10.1109/ASP-DAC47756.2020.9045351,

https://backend.orbit.dtu.dk/ws/files/199809995/verifypat.pdf