Abstract

Computer architectures used in safety-critical domains are subjected to worst-case execution time analysis. The presence of performance-driven microarchitectures may trigger undesired timing phenomena, called timing anomalies, and complicate the timing analysis. This paper investigates pipelines specifically designed to simplify the worst-case execution time analysis (also called predictable pipelines). We propose formal and executable models of four research-oriented pipelines and one industrial pipeline to validate some of their claims related to their timing behavior. We indeed validate, via bounded model checking, the absence of a type of timing anomalies called amplification timing anomalies, or its potential presence by identifying prerequisite to situations where they can occur.<br


Original document

The different versions of the original document can be found in:

http://dx.doi.org/10.1109/asp-dac47756.2020.9045351
https://backend.orbit.dtu.dk/ws/files/199809995/verifypat.pdf,
https://orbit.dtu.dk/en/publications/formal-semantics-of-predictable-pipelines-a-comparative-study,
https://staging.orbit.dtic.dk/en/publications/formal-semantics-of-predictable-pipelines-a-comparative-study,
https://academic.microsoft.com/#/detail/3013903002
https://doi.org/10.1109/ASP-DAC47756.2020.9045351,
https://backend.orbit.dtu.dk/ws/files/199809995/verifypat.pdf
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Document information

Published on 01/01/2020

Volume 2020, 2020
DOI: 10.1109/asp-dac47756.2020.9045351
Licence: CC BY-NC-SA license

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