A Finite State Machine modeling language and the associated tools allowing fast prototyping for FPGA devices

Abstract

International audience; The VHDL hardware description language is commonly used to describe Finite State Machine(FSM) models to be implemented on Field Programmable Gate Array(FPGA) devices. However, its versatility permits to describe behaviors that deviate from a true FSM leading to systems that are complex to prove, to document and to maintain. The purpose of this work is to propose a language and the associated tools to create FSMs through a dedicated and intuitive textual description. This language is inspired by the dot language used in Graphviz, a tool to define graphs, and adds all the necessary elements required to describe complex FSM models (using for instance memorized or non memorized actions and actions on states or transitions). Moreover some additional elements are proposed to enrich the standard FSM model such as the genericity that permits to define simultaneously multiple states, transitions or actions using a generative description. A multi-platform open source JAVA program named FSMPro-cess [1] is introduced. Based on the ANTLR parser generator, it achieves the automatic generation of all the required .vhdl files (component, package, instantiation example and testbench) and a .dot file that is used to generate an always up-to-date graphical representation of the model (hence its documentation). This tool also supports simple model checking and integration of additional VHDL code. It can be used conjointly with version control systems and is coupled with the open source GHDL simulator to allow fast prototyping. It can be used either with its Graphical User Interface either as a command line compiler for integration in makefiles.