Implementing an ISR defense on a MIPS architecture

Abstract

Code injection attacks are an undeniable threat in today's cyberworld. Instruction Set Randomization (ISR) was initially proposed in 2003. This technique was designed to protect systems against code injection attacks by creating an unique instruction set for each machine, thanks to randomization. It is a promising technique in the growing embedded system and Internet of Things (IoT) devices ecosystem, where the lack of complex memory management make these devices more vulnerable. However, most of ISR implementations up to day are entirely software based. In this work, we implement hardware support for an ISR defense on an 32 bits, 5 pipeline stages MIPS processor (which is an embedded system compatible architecture). Two obfuscation schemes were implemented, one based on XOR encryption and the other on transposition. The hardware implementation was tested under synthetic code injection attacks and results shows the effectiveness of the defense using both encryption circuits.

Original document

The different versions of the original document can be found in:

• http://sedici.unlp.edu.ar/bitstream/handle/10915/65514/Documento_completo.pdf?sequence=1 under the license cc-by-sa

• http://sedici.unlp.edu.ar/handle/10915/65514,

https://dblp.uni-trier.de/db/conf/clei/clei2017.html#SanchoB17,

https://ieeexplore.ieee.org/document/8226448,

https://academic.microsoft.com/#/detail/2779900600

• http://xplorestaging.ieee.org/ielx7/8171462/8226362/08226448.pdf?arnumber=8226448,

http://dx.doi.org/10.1109/clei.2017.8226448