Electrical-level synthesis of pipeline ADCs

Abstract

This paper presents a design tool for the synthesis of pipeline ADCs which is able to optimally map high-level converter specifications, such as the required effective resolution, onto electrical-level parameters, i.e., transistor sizes and biasing conditions. It is based on the combination of a behavioural simulator for performance evaluation, accurate models of the converter components, and an optimization algorithm to minimize the power and area consumption of the circuit solution. The design procedure is herein demonstrated with the complete design of a 0.13 mum CMOS 10 bits@60MS/s pipeline ADC, which only consumes 11.3 mW from a 1.2 V supply voltage. A close agreement between behavioural- and electrical-level simulations is obtained with only 0.2 bit deviation on the measured ENOB. Ministerio de Educación y Ciencia TEC2006-03022 Junta de Andalucía TIC-02818

Original document

The different versions of the original document can be found in:

• https://idus.us.es/xmlui/handle//11441/89922 under the license http://creativecommons.org/licenses/by-nc-nd/4.0/

• http://xplorestaging.ieee.org/ielx5/4723905/4745943/04746348.pdf?arnumber=4746348,

http://dx.doi.org/10.1109/apccas.2008.4746348

• https://dblp.uni-trier.de/db/conf/apccas/apccas2008.html#Ruiz-AmayaDR08,

http://yadda.icm.edu.pl/yadda/element/bwmeta1.element.ieee-000004746348,

https://idus.us.es/handle/11441/89922,

https://academic.microsoft.com/#/detail/2133821653