Synchronised 4-Phase Resonant Power Clock Supply for Energy Efficient Adiabatic Logic

Abstract

International audience; Adiabatic logic is an alternative architecture design style to reduce the power consumption of digital cores by using AC power supply instead of DC ones. The energy saving of the digital gates is strongly related to the efficiency of adiabatic AC power supplies. In this paper, we propose a resonant reversible power-clock supply design with four different phases. The resonance deviation between the four power-clock supplies is synchronized thanks to 12 control signals (3 controls signals per power-clock supply). We derive the energy dissipation of a 4-stage PFAL pipeline circuit supplied with the proposed resonant powerclock supply, which can dissipate up to 2.9 times less energy than a non-adiabatic CMOS pipeline.

Original document

The different versions of the original document can be found in:

• https://hal-lirmm.ccsd.cnrs.fr/lirmm-01768831

• http://xplorestaging.ieee.org/ielx7/8121842/8123622/08123661.pdf?arnumber=8123661,

http://dx.doi.org/10.1109/icrc.2017.8123661

• https://hal-lirmm.ccsd.cnrs.fr/lirmm-01768831,

https://dblp.uni-trier.de/db/conf/icrc/icrc2017.html#JeanniotPNAT17,

https://academic.microsoft.com/#/detail/2775246436