Abstract
IEEE International Symposium on Circuits and Systems, pp. 2258 – 2261, Seattle, EUA A low-power 1.2 V 6-bit 1-GS/s time-interleaved pipeline ADC designed in 130 nm CMOS is described. It is based on a new 2-channel 1.5-bit MDAC that performs openloop residue amplification using a shared amplifier employing local-feedback. Time mismatches between channels are highly attenuated, simply by using two passive front-end Sample-and-Hold circuits, with dedicated switch-linearization control circuits, driven by a single clock phase. Simulated results of the ADC achieve 5.35-bit ENOB, with 20 mW and without requiring any gain control/calibration scheme.
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Published on 01/01/2008
Volume 2008, 2008
DOI: 10.1109/iscas.2008.4541903
Licence: CC BY-NC-SA license
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