A Design for the 178-MHz WXGA 30-fps Optical Flow Processor Based on the HOE Algorithm

Abstract

We propose an optical flow processor, which allows real-Time processing of WXGA 30-fps at 178.3 MHz. By introducing the SOR method and a pipeline operation for the Gauss-Seidel method to the iterative flow calculation, computational complexity can be reduced to 14.5% when compared to the previous HOE processor. We decreased the area of the embedded memory by using the image division method, applying line memory, and optimizing the computation word length. The core size of the designed processor is 16.82 mm2 in 90 nm process technology, which is approximately 5% of the previous HOE processor. The processor can operate completely in parallel, which ensures high-resolution scalability. © 2015 IEEE.

18th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2015; Belgrade; Serbia; 22 April 2015 through 24 April 2015; Category numberE5519; Code 116884

Original document

The different versions of the original document can be found in:

• http://hdl.handle.net/2297/44879

• https://kanazawa-u.repo.nii.ac.jp/?action=repository_action_common_download&item_id=9208&item_no=1&attribute_id=26&file_no=1

• http://xplorestaging.ieee.org/ielx7/7193738/7195649/07195664.pdf?arnumber=7195664,

http://dx.doi.org/10.1109/ddecs.2015.36

• https://dblp.uni-trier.de/db/conf/ddecs/ddecs2015.html#MatsumuraKIM15,

https://academic.microsoft.com/#/detail/1502956333