A high-speed reconfigurable architecture for heterogeneous multimodal packet traffic generation

Abstract

Traffic modeling plays a key role in the study of packet switching systems, such as Internet routers. As line rates increase towards tens of gigabits per second, the duration of individual packets decreases, rendering real-time traffic generation a fundamental engineering challenge. In evaluation of these systems, it is critical to reproduce traffic conditions that approximate the target environment. Additionally, the ability to generate traffic flows that establish the limitations of a given algorithm or architecture is highly desirable. To address these issues, we propose a reconfigurable high-speed hardware architecture for heterogeneous multimodal packet generation. FPGA results demonstrate the scalability and flexibility of the proposed framework

Original document

The different versions of the original document can be found in:

• http://www.ece.utk.edu/%7Eitamar/Papers/MWSCAS2005_3297.pdf

• http://xplorestaging.ieee.org/ielx5/10622/33557/01594308.pdf?arnumber=1594308,

http://dx.doi.org/10.1109/mwscas.2005.1594308

• http://yadda.icm.edu.pl/yadda/element/bwmeta1.element.ieee-000001594308,

https://academic.microsoft.com/#/detail/2123973714