Abstract

Increasing dynamic variability with technology scaling has made it essential to incorporate large design-time timing margins to ensure yield and reliable operation. Online techniques for timing error resilience help recover timing margins, improving performance and/or power consumption. This paper presents TIMBER, a technique for online timing error resilience that masks timing errors by borrowing time from successive pipeline stages. TIMBER-based error masking can recover timing margins without instruction replay or roll-back support. Two sequential circuit elements --- TIMBER flip-flop and TIMBER latch --- that implement error masking based on time-borrowing are described. Both circuit elements are validated using corner-case circuit simulations, and the overhead and trade-offs of TIMBER-based error masking are evaluated on an industrial processor.


Original document

The different versions of the original document can be found in:

http://www.ece.rice.edu/~kmram/publications/timber.pdf,
https://dblp.uni-trier.de/db/conf/date/date2010.html#ChoudhuryCMA10a,
http://yadda.icm.edu.pl/yadda/element/bwmeta1.element.ieee-000005457058,
https://dl.acm.org/citation.cfm?id=1870926.1871301,
http://www-ece.rice.edu/%7ekmram/publications/timber.pdf,
https://academic.microsoft.com/#/detail/2118880665
http://dx.doi.org/10.1109/date.2010.5457058
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Document information

Published on 01/01/2013

Volume 2013, 2013
DOI: 10.1109/date.2010.5457058
Licence: CC BY-NC-SA license

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