Adaptive Clock Scheduling for pipelined structures

Abstract

This paper introduces a technique called Adaptive Inverter Chain Based Clock Scheduling, which can observe and compensate delay variations in pipelined structures. The main idea behind the method is to expose the data and the clock to the same variations such that the register data sampling process is not disturbed by variations. The proposed scheme also includes a mechanism to detect time failures and to take counter actions to recover from such situations. When compared with other state of the art proposals, which require the augmentation of the registers, our proposal requires a relative smaller area overhead due to the fact that it is focussed on clock and not on data. Moreover our simulations indicate that, depending on the specific delay variations and pipeline logic delay sensitivity to input data patterns, it can enable an up to 46% performance improvement.