Generic Pipelined Processor Modeling and High Performance Cycle-Accurate Simulator Generation

Abstract

Detailed modeling of processors and high performance cycle-accurate simulators are essential for today's hardware and software design. These problems are challenging enough by themselves and have seen many previous research efforts. Addressing both simultaneously is even more challenging, with many existing approaches focusing on one over another. In this paper, we propose the Reduced Colored Petri Net (RCPN) model that has two advantages: first, it offers a very simple and intuitive way of modeling pipelined processors; second, it can generate high performance cycle-accurate simulators. RCPN benefits from all the useful features of Colored Petri Nets without suffering from their exponential growth in complexity. RCPN processor models are very intuitive since they are a mirror image of the processor pipeline block diagram. Furthermore, in our experiments on the generated cycle-accurate simulators for XScale and StrongArm processor models, we achieved an order of magnitude (~15 times) speedup over the popular SimpleScalar ARM simulator.

Comment: Submitted on behalf of EDAA (http://www.edaa.com/)

Original document

The different versions of the original document can be found in:

• http://arxiv.org/abs/0710.4643

• http://arxiv.org/pdf/0710.4643

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• https://hal.archives-ouvertes.fr/hal-00181210,

https://hal.archives-ouvertes.fr/hal-00181210/document,

https://hal.archives-ouvertes.fr/hal-00181210/file/228820786.pdf