Optimal power/performance pipelining for error resilient processors

Abstract

Timing speculation has been proposed as a technique for maximizing the energy efficiency of processors with minimal loss in performance. A typical implementation of timing speculation involves speculatively reducing the voltage of a processor to a point where errors are possible but rare, and employing an error recovery mechanism to ensure correct functionality. This allows significant energy savings with a small recovery overhead.

Original document

The different versions of the original document can be found in:

• https://www.ideals.illinois.edu/bitstream/2142/16791/2/zea_nicolas.pdf

• http://xplorestaging.ieee.org/ielx5/5640356/5647518/05647702.pdf?arnumber=5647702,

http://dx.doi.org/10.1109/iccd.2010.5647702

• https://experts.umn.edu/en/publications/optimal-powerperformance-pipelining-for-error-resilient-processor,

http://yadda.icm.edu.pl/yadda/element/bwmeta1.element.ieee-000005647702,

https://www.ideals.illinois.edu/handle/2142/16791,

https://dblp.uni-trier.de/db/conf/iccd/iccd2010.html#ZeaSAK10,

https://experts.illinois.edu/en/publications/optimal-powerperformance-pipelining-for-error-resilient-processor,

http://www.ece.umn.edu/users/jsartori/papers/iccd10.pdf,

https://www.ideals.illinois.edu/bitstream/2142/16791/2/zea_nicolas.pdf,

https://academic.microsoft.com/#/detail/2061130129