A multi-format floating-point multiplier for power-efficient operations

Abstract

In this work, we present a radix-16 multi-format multiplier to multiply 64-bit unsigned integer operands, double-precision and single-precision operands. The multiplier is sectioned in two lanes such that two single-precision multiplications can be computed in parallel. Radix-16 is chosen for the reduced number of partial products and the resulting power savings. The experimental results show that high power efficiency is obtained by issuing two single-precision multiplications per cycle. Moreover, by converting the double-precision numbers which fit to single-precision, further energy can be saved.

Original document

The different versions of the original document can be found in:

• https://backend.orbit.dtu.dk/ws/files/140637420/PID4894991.pdf

• http://xplorestaging.ieee.org/ielx7/8170502/8225969/08226076.pdf?arnumber=8226076,

http://dx.doi.org/10.1109/socc.2017.8226076

• https://core.ac.uk/display/141514386,

https://dblp.uni-trier.de/db/conf/socc/socc2017.html#Nannarelli17,

https://academic.microsoft.com/#/detail/2777846885

• https://orbit.dtu.dk/en/publications/2d2ce322-6d6a-4d05-9036-3102f490a1c3,

https://doi.org/10.1109/SOCC.2017.8226076,

https://backend.orbit.dtu.dk/ws/files/140637420/PID4894991.pdf