HPAZ: a High-throughput Pipeline Architecture of ZUC in Hardware

Abstract

In this paper, we propose a high-throughput pipeline architecture of the stream cipher ZUC which has been included in the security portfolio of 3GPP LTE-Advanced. In the literature, the schema with the highest throughput only implements the working stage of ZUC. The schemas which implement ZUC completely can only achieve a much lower throughput, since a self-feedback loop in the critical path significantly reduces the operating frequency. In this paper we design a mixed two-stage pipeline architecture which not only completely implements ZUC but also significantly raises the throughput. We have implemented our architecture in FPGAs and ASICs. In FPGAs platform, the new architecture increases the throughput by 45%, compared with the latest work, and particularly the new architecture also saves nearly 12% of hardware resources. In the 65nm ASIC technology, the throughput of the new design can up to 80Gbps, which is 2.7 times faster than the fastest one in the literature, in particular, it also saves at least 40% of hardware resources. In addition to the academic design, compared with the fastest commercial design, the new architecture doubles the throughput of that. To the best of our knowledge, this evaluation result is so far the best outcome.

Original document

The different versions of the original document can be found in:

• http://dx.doi.org/10.3850/9783981537079_0557

• http://eprint.iacr.org/2013/461.pdf

• https://dblp.uni-trier.de/db/conf/date/date2016.html#LiuZMLJ16,

https://eprint.iacr.org/2013/461.pdf,

https://academic.microsoft.com/#/detail/2346023863