Latest revision as of 17:23, 3 February 2021

Abstract

Conventional set-associative data cache accesses waste energy since tag and data arrays of several ways are simultaneously accessed to sustain pipeline speed. Different access techniques to avoid activating all cache ways have been previously proposed in an effort to reduce energy usage. However, a problem that many of these access techniques have in common is that they need to access different cache memory portions in a sequential manner, which is difficult to support with standard synchronous SRAM memory.We propose the speculative halt-tag access (SHA) approach, which accesses low-order tag bits, i.e., the halt tag, in the address generation stage instead of the SRAM access stage to eliminate accesses to cache ways that cannot possibly contain the data. The key feature of our SHA approach is that it determines which tag and data arrays need to be accessed early enough for conventional SRAMs to be used. We evaluate the SHA approach using a 65-nm processor implementation running MiBench benchmarks and find that it on average reduces data access energy by 25.6%.

Original document

The different versions of the original document can be found in:

• http://dx.doi.org/10.3850/9783981537079_0663

• http://www.cs.fsu.edu/%7Ewhalley/papers/date16.pdf

• https://dblp.uni-trier.de/db/conf/date/date2016.html#MoreauBSWL16,

http://publications.lib.chalmers.se/records/fulltext/233173/local_233173.pdf,

http://www.cs.fsu.edu/~whalley/papers/date16.pdf,

https://research.chalmers.se/en/publication/233173,

http://www.diva-portal.org/smash/record.jsf?pid=diva2:1039666,

http://uu.diva-portal.org/smash/record.jsf?pid=diva2:1039666,

https://core.ac.uk/display/103836494,

https://academic.microsoft.com/#/detail/2295977398