Latest revision as of 10:19, 8 February 2021

Abstract

In this paper we present how Intel's Single-Chip-Cloud processor behaves for parallel macro pipeline applications. Subsets of the SCC's available cores can be arranged as a pipeline where each core processes one stage of the overall workload. Each of the independent cores processes a small part of a larger task and feeds the following core with new data after it finishes its work. Our case-study is a parallel rendering system which renders successive images and applies different filters on them. On normal graphics adapters this is usually done in multiple cycles, we do this in a single pipeline pass. We show that we can achieve a significant speedup by using multiple parallel pipelines on the SCC. We show that we can further improve performance by using SCC's controlling PC in conjunction with the SCC. We also identify aspects of the SCC that hinder the overall performance, mainly the lack of local memory banks for each core on the SCC. The results presented in this paper are not limited to only image processing, but users could expect similar experiences where macro pipelining is used in other applications on the SCC.

Original document

The different versions of the original document can be found in:

• http://dx.doi.org/10.1109/IPDPSW.2013.136

• http://xplorestaging.ieee.org/ielx7/6603430/6650854/06650872.pdf?arnumber=6650872,

http://dx.doi.org/10.1109/ipdpsw.2013.136

• https://dblp.uni-trier.de/db/conf/ipps/ipdps2013w.html#SussSMP13,

https://ieeexplore.ieee.org/document/6650872,

https://ris.uni-paderborn.de/publication/1787,

https://dl.acm.org/citation.cfm?id=2510648.2510791,

https://doi.org/10.1109/IPDPSW.2013.136,

http://ieeexplore.ieee.org/document/6650872,

https://www.computer.org/csdl/proceedings/ipdpsw/2013/4979/00/4979a064.pdf,

https://academic.microsoft.com/#/detail/2051374399