Latest revision as of 09:59, 8 February 2021

Abstract

In this paper, an error analysis is presented to aid the design of a pipeline multi-bit front-end stage. It is demonstrated and quantified how the capacitor matching requirement can be reduced in high-resolution pipeline ADCs. The paper continues by analyzing the optimal design for low power of the scaled back-end stages. Finally, a model is proposed to estimate the power per stage, and hence total power consumption of the pipeline ADC.

Original document

The different versions of the original document can be found in:

• https://research.tue.nl/nl/publications/design-and-optimization-of-multibit-frontend-stage-and-scaled-backend-stages-of-pipelined-adcs(d6687039-1ad7-4e4b-ac3a-23086c61b091).html

• http://xplorestaging.ieee.org/ielx5/9898/31469/01464999.pdf?arnumber=1464999,

http://dx.doi.org/10.1109/iscas.2005.1464999

• https://ieeexplore.ieee.org/xpl/freeabs_all.jsp?arnumber=1464999,

http://ieeexplore.ieee.org/xpl/freeabs_all.jsp?arnumber=1464999,

https://dblp.uni-trier.de/db/conf/iscas/iscas2005-3.html#QuinnR05a,

http://dx.doi.org/10.1109/ISCAS.2005.1464999,

https://doi.org/10.1109/ISCAS.2005.1464999,

http://doi.org/10.1109/ISCAS.2005.1464999,

https://www.narcis.nl/publication/RecordID/oai%3Apure.tue.nl%3Apublications%2Fd6687039-1ad7-4e4b-ac3a-23086c61b091,

https://academic.microsoft.com/#/detail/2171623652