(Created page with " == Abstract == Flip-flops and latches are two options to construct pipelines in digital integrated circuits (ICs). In this paper, the implications for converting a flip-flop...") |
m (Scipediacontent moved page Draft Content 347591733 to Fatemi et al 2018a) |
(No difference)
| |
Latest revision as of 09:54, 8 February 2021
Abstract
Flip-flops and latches are two options to construct pipelines in digital integrated circuits (ICs). In this paper, the implications for converting a flip-flop based design to a latch-based design are investigated by performing timing and power analysis. Design flows are also proposed to convert a flip-flop based design to a latch-based design as well as a latch/flip-flop-mixed design. With a new retiming strategy, the optimum operating condition is identified for both the latch based design and the mixed design, where the maximum time borrowing or performance enhancement can be obtained. Compared to the flip-flop based design, 48% and 45% frequency boosting are achieved by the latch based design and the mixed design, respectively. While maintaining the same performance as the flip-flop based design with the aid of supply voltage scaling, the latch based design and the mixed design reduce the power consumption by 21% and 16%, respectively, in an industrial 28-nm FDSOI CMOS technology.
Original document
The different versions of the original document can be found in:
Document information
Published on 08/05/18
Accepted on 08/05/18
Submitted on 08/05/18
Volume 2018, 2018
DOI: 10.1109/isqed.2018.8357308
Licence: CC BY-NC-SA license
Share this document
Keywords
claim authorship
Are you one of the authors of this document?