Latest revision as of 09:39, 8 February 2021

Abstract

utonomous driving is disrupting conventional automotive development. Underlying reasons include control unit consolidation, the use of components originally developed for the consumer market, and the large amount of data that must be processed. For instance, Audi's zFAS or NVIDIA's Xavier platform integrate GPUs, custom accelerators, and CPUs within a single domain controller to perform sensor fusion, processing, and decision making. The communication between these heterogeneous components and the algorithms for Advanced Driver Assistance Systems and Autonomous Driving require low latency and huge memory bandwidth, bringing the Memory Wall from high-performance computing in data centers directly to our cars. In this paper we discuss these and other requirements in using DRAM for near-term autonomous driving architectures.

Original document

The different versions of the original document can be found in:

• http://dx.doi.org/10.1145/3240302.3240322 under the license http://www.acm.org/publications/policies/copyright_policy#Background

• http://publica.fraunhofer.de/documents/N-534994.html

• http://dl.acm.org/ft_gateway.cfm?id=3240322&ftid=2028120&dwn=1,

http://dx.doi.org/10.1145/3240302.3240322 under the license http://www.acm.org/publications/policies/copyright_policy#Background

• https://dblp.uni-trier.de/db/conf/memsys/memsys2018.html#0001MSDWW18,

https://dl.acm.org/citation.cfm?id=3240322,

https://academic.microsoft.com/#/detail/2908483391