Latest revision as of 21:49, 3 February 2021

Abstract

This paper presents a novel technique to minimize the total power consumption of a synchronous linear pipeline circuit by exploiting extra slacks available in some stages of the pipeline. The key idea is to utilize soft-edge flip-flops to enable time borrowing between stages of a linear pipeline in order to provide the timing-critical stages with more time to complete their computations. Time borrowing, in conjunction with keeping the clock frequency unchanged, gives rise to a positive timing slack in each pipeline stage. The slack is subsequently utilized to minimize the circuit power consumption by reducing the supply voltage level. We formulate and solve the problem of optimally selecting the transparency window of the soft-edge flip-flops and choosing the minimum supply voltage level for the pipeline circuit as a quadratic program, thereby minimizing the power consumption of the linear pipeline circuit under a clock frequency constraint. Experimental results prove the efficacy of the problem formulation and solution technique.

Original document

The different versions of the original document can be found in:

• http://atrak.usc.edu/~behnam/papers/islped08.pdf

• http://sportlab.usc.edu/~behnam/papers/islped08.pdf,

http://core.ac.uk/display/23787217,

http://yadda.icm.edu.pl/yadda/element/bwmeta1.element.ieee-000005529075,

https://dblp.uni-trier.de/db/conf/islped/islped2008.html#GhasemazarAP08,

https://doi.acm.org/10.1145/1393921.1393935,

https://dl.acm.org/citation.cfm?id=1393921.1393935,

https://academic.microsoft.com/#/detail/2157684267

• http://dl.acm.org/ft_gateway.cfm?id=1393935&ftid=542316&dwn=1,

http://dx.doi.org/10.1145/1393921.1393935