Latest revision as of 19:11, 3 February 2021

Abstract

With growing semiconductor integration, the reliability of individual transistors is expected to rapidly decline in future technology generations. In such a scenario, processors would need to be equipped with fault tolerance mechanisms to tolerate in-field silicon defects. Periodic online testing is a popular technique to detect such failures; however, it tends to impose a heavy testing penalty. In this paper, we propose an adaptive online testing framework to significantly reduce the testing overhead. The proposed approach is unique in its ability to assess the hardware health and apply suitably detailed tests. Thus, a significant chunk of the testing time can be saved for the healthy components. We further extend the framework to work with the StageNet CMP fabric, which provides the flexibility to group together pipeline stages with similar health conditions, thereby reducing the overall testing burden. For a modest 2.6% sensor area overhead, the proposed scheme was able to achieve an 80% reduction in software test instructions over the lifetime of a 16-core CMP.

Original document

The different versions of the original document can be found in:

• http://cccp.eecs.umich.edu/papers/sgupta-iccd09.pdf

• http://web.eecs.umich.edu/~shangupt/publications/sgupta-iccd09.pdf,

http://cccp.eecs.umich.edu/papers/sgupta-iccd09.pdf,

http://yadda.icm.edu.pl/yadda/element/bwmeta1.element.ieee-000005413132,

https://dblp.uni-trier.de/db/conf/iccd/iccd2009.html#GuptaAFM09,

https://dl.acm.org/citation.cfm?id=1792354.1792420,

https://academic.microsoft.com/#/detail/2095683370

• http://xplorestaging.ieee.org/ielx5/5406656/5413104/05413132.pdf?arnumber=5413132,

http://dx.doi.org/10.1109/iccd.2009.5413132