Latest revision as of 17:54, 3 February 2021

Abstract

This paper presents a detailed analysis of an architectural pipeline scheme for Quantum-dot Cellular Automata (QCA); this scheme utilizes the so-called Bennett clocking for attaining high throughput and low power dissipation. In this arrangement, computation stages (utilizing Bennett clocking) and memory stages combine the low power dissipation of reversible computing with the high throughput feature of a pipeline. An example of the application of the proposed scheme to an XOR tree circuit (parity generator) is presented; a detailed analysis of throughput and power consumption is provided to show the effectiveness of the proposed architectural solution for QCA.

Original document

The different versions of the original document can be found in:

• http://dftgroup.uniroma2.it/lib/exe/fetch.php?media=nano2010.pdf

• http://xplorestaging.ieee.org/ielx5/5506521/5510921/05510931.pdf?arnumber=5510931,

http://dx.doi.org/10.1109/nanoarch.2010.5510931

• http://yadda.icm.edu.pl/yadda/element/bwmeta1.element.ieee-000005510931,

https://dl.acm.org/citation.cfm?id=1835964,

http://dftgroup.uniroma2.it/data/media/nano2010.pdf,

https://dblp.uni-trier.de/db/conf/nanoarch/nanoarch2010.html#OttaviPDSKL10,

https://ieeexplore.ieee.org/document/5510931,

https://art.torvergata.it/handle/2108/23820,

https://academic.microsoft.com/#/detail/2058216106