Latest revision as of 17:08, 3 February 2021

Abstract

Hardware accelerators are common in embedded systems that have high performance requirements but must still operate within stringent energy constraints. To facilitate short time-to-market and reduced non-recurring engineering costs, automatic systems that can rapidly generate hardware bearing both power and performance in mind are extremely attractive. This paper proposes the BLADES (Better-than-worst-case Loop Accelerator Design) system for automatically designing self-tuning hardware accelerators that dynamically select their best operating frequency and voltage based on environmental conditions, silicon variation, and input data characteristics. Errors in operation are detected by Razor flip-flops, and recovery is initiated. The architecture efficiently supports detection, rollback, and recovery to provide a highly adaptable and configurable loop accelerator. The overhead of deploying Razor flip-flops is significantly reduced by automatically chaining primitive computation operations together. Results on a range of loop accelerators show average energy savings of 32% gained by voltage scaling below the nominal supply voltage.

Original document

The different versions of the original document can be found in:

• http://cccp.eecs.umich.edu/papers/gdasika-dac08.pdf

• http://cccp.eecs.umich.edu/papers/gdasika-dac08.pdf,

https://dblp.uni-trier.de/db/conf/dac/dac2008.html#DasikaDFMB08,

http://yadda.icm.edu.pl/yadda/element/bwmeta1.element.ieee-000004555946,

https://dl.acm.org/citation.cfm?id=1391694,

https://doi.acm.org/10.1145/1391469.1391694,

https://academic.microsoft.com/#/detail/2100215874

• http://dl.acm.org/ft_gateway.cfm?id=1391694&ftid=529276&dwn=1,

http://dx.doi.org/10.1145/1391469.1391694