Latest revision as of 08:11, 2 February 2021

Abstract

Conference of 10th IEEE International Symposium on Industrial Embedded Systems, SIES 2015 ; Conference Date: 8 June 2015 Through 10 June 2015; Conference Code:116797; International audience; Many-core architectures are promising hardware to design hard real-time systems as they are based on simpler and thus more predictable processors than multi-core systems. However, the worst-case behavior of the Network-on-Chip (NoC) for both inter-core and core to external memories or peripherals communications must be established. Several NoCs targeting hard real-time systems, made of specific hardware extensions, have been designed. However, none of these extensions are currently available in commercially existing NoC-based many-core architectures, that instead rely on wormhole switching with round-robin arbitration. In this paper, we thus demonstrate three properties of such NoC-based wormhole networks to identify worst-case scenarios and reduce the pessimism when modeling flows in contentions. We then describe and evaluate an algorithm to compute Worst-Case Traversal Time (WCTT) of flows that uses these properties. In particular, our results show that the pessimism can be reduced up to 50% compared to current state-of-the-art real-time packet schedulability analysis.

Original document

The different versions of the original document can be found in:

• https://hal-cea.archives-ouvertes.fr/cea-01836859

• http://ieeexplore.ieee.org/lpdocs/epic03/wrapper.htm?arnumber=7185041,

https://doi.org/10.1109/SIES.2015.7185041,

http://doi.org/10.1109/SIES.2015.7185041,

https://ieeexplore.ieee.org/lpdocs/epic03/wrapper.htm?arnumber=7185041,

https://dblp.uni-trier.de/db/conf/sies/sies2015.html#AbdallahJEF15,

https://academic.microsoft.com/#/detail/1510648976

• http://xplorestaging.ieee.org/ielx7/7164234/7185026/07185041.pdf?arnumber=7185041,

http://dx.doi.org/10.1109/sies.2015.7185041