Latest revision as of 07:40, 2 February 2021

Abstract

The configurable routing in asynchronous FPGAs accounts for 80-90% of the total area and consumes 80-90% of the total power. This paper presents an asynchronous FPGA that applies two techniques to reduce power consumption. First, the routing is altered to use two-phase logic rather than four-phase logic. Second, enable (acknowledge) signals are voltage scaled such that the overall FPGA performance is not affected. The resulting FPGA is evaluated across eight of the MCNC LGSynth93 benchmarks. This FPGA consumes up to 60% less power than a conventional asynchronous FPGA. In addition, the extra slack provided by two-phase routing increases the throughput of some benchmarks by up to 70%. The additional hardware required to implement the low-power techniques increases the total area by only 12%.

Original document

The different versions of the original document can be found in:

• http://vlsi.cornell.edu/~rajit/ps/fpga2p.pdf

• http://xplorestaging.ieee.org/ielx5/5476381/5476957/05476972.pdf?arnumber=5476972,

http://dx.doi.org/10.1109/async.2010.23

• http://yadda.icm.edu.pl/yadda/element/bwmeta1.element.ieee-000005476972,

http://ieeexplore.ieee.org/articleDetails.jsp?arnumber=5476972,

https://dl.acm.org/citation.cfm?id=1826165.1826385,

https://dblp.uni-trier.de/db/conf/async/async2010.html#LaFriedaHM10,

https://academic.microsoft.com/#/detail/1982876335