Latest revision as of 04:25, 2 February 2021

Abstract

We present a technique to automatically synthesize a multithreaded in-order pipeline from a high-level unpipelined datapath specification. This work extends the previously proposed transactional specification (T-spec) and synthesis technology (T-piper). The technique not only works with instruction processors but also flexible enough to accept any sequential datapath. It maintains previously proposed non-threaded pipeline features and is enhanced with multithreading features. We report a design space exploration study of 32 multithreaded x86 processor pipelines, all synthesized from a single T-spec.

Original document

The different versions of the original document can be found in:

• http://users.ece.cmu.edu/~jhoe/distribution/2010/dac10.pdf

• http://users.ece.cmu.edu/~jhoe/distribution/2010/dac10.pdf,

https://dblp.uni-trier.de/db/conf/dac/dac2010.html#NurvitadhiHLK10,

http://yadda.icm.edu.pl/yadda/element/bwmeta1.element.ieee-000005523415,

https://www.researchgate.net/profile/Shih-Lien_Lu/publication/221059221_Automatic_multithreaded_pipeline_synthesis_from_transactional_datapath_specifications/links/0fcfd50933e984e1c7000000.pdf,

https://academic.microsoft.com/#/detail/2043735637

• http://dl.acm.org/ft_gateway.cfm?id=1837356&ftid=827244&dwn=1,

http://dx.doi.org/10.1145/1837274.1837356