Latest revision as of 21:49, 1 February 2021

Abstract

The effect of Single-Event Transients (SETs) (at a combinational node of a design) on the system reliability is becoming a big concern for ICs manufactured using advanced technologies. An SET at a node of combinational part may cause a transient pulse at the input of a flip-flop and consequently is latched in the flip-flop and generates a soft-error. When an SET conjoined with a transition at a node along a critical path of the combinational part of a design, a transient delay fault may occur at the input of a flip-flop. On the other hand, increasing pipeline depth and using low power techniques such as multi-level power supply, and multi-threshold transistor convert almost all paths in a circuit to critical ones. Thus, studying the behavior of the SET in these kinds of circuits needs special attention. This paper studies the dynamic behavior of a circuit with massive critical paths in the presence of an SET. We also propose a novel flip-flop architecture to mitigate the effects of such SETs in combinational circuits. Furthermore, the proposed architecture can tolerant a Single Event Upset (SEU) caused by particle strike on the internal nodes of a flip-flop.

Original document

The different versions of the original document can be found in:

• http://hdl.handle.net/11583/1499972

• https://iris.polito.it/retrieve/handle/11583/1499972/47091/2006-ETS-SEU.pdf

• http://xplorestaging.ieee.org/ielx5/10839/34157/01628150.pdf?arnumber=1628150,

http://dx.doi.org/10.1109/ets.2006.41

• http://yadda.icm.edu.pl/yadda/element/bwmeta1.element.ieee-000001628150,

https://iris.polito.it/handle/11583/1499972,

https://dblp.uni-trier.de/db/conf/ets/ets2006.html#HosseinabadyLNCBP06,

https://dl.acm.org/citation.cfm?id=1136035,

https://ieeexplore.ieee.org/lpdocs/epic03/wrapper.htm?arnumber=1628150,

https://www.researchgate.net/profile/Stefano_Di_Carlo/publication/232616256_Single-Event_Upset_Analysis_and_Protection_in_High_Speed_Circuits/links/0912f50b3fdf7e89a8000000.pdf,

http://porto.polito.it/1499972,

https://www.computer.org/csdl/proceedings/ets/2006/2566/00/25660029.pdf,

https://academic.microsoft.com/#/detail/2168546702