Latest revision as of 20:43, 1 February 2021

Abstract

Exception handling is one of the most complicated issues in pipelined processors. Several incomplete instructions are in process in the pipeline at any instant in time, and an exception may cause a state change of the processor (Hennessy and Patterson, 2002) at any such instant. Prior research efforts have proposed mechanisms for precise exception handling, but it is difficult to achieve precise exception handling in minimal area as required by embedded and processing-in-memory systems. This paper presents a correct and efficient exception handling scheme with a modest hardware resource. The presented idea maintains precise exception handling in the case of discrete control flow and has been implemented in 90 nm technology.

Original document

The different versions of the original document can be found in:

• http://www.isi.edu/~draper/papers/mwscas08_kang.pdf

• http://www.isi.edu/~draper/papers/mwscas08_kang.pdf,

http://yadda.icm.edu.pl/yadda/element/bwmeta1.element.ieee-000004616852,

https://academic.microsoft.com/#/detail/2169998846

• http://xplorestaging.ieee.org/ielx5/4603800/4616714/04616852.pdf?arnumber=4616852,

http://dx.doi.org/10.1109/mwscas.2008.4616852