Latest revision as of 16:29, 1 February 2021

Abstract

In this paper we propose application specific instruction set processors with heterogeneous multiple pipelines to efficiently exploit the available parallelism at instruction level. We have developed a design system based on the Thumb processor architecture. Given an application specified in C language, the design system can generate a processor with a number of pipelines specifically suitable to the application, and the parallel code associated with the processor. Each pipeline in such a processor is customized, and implements its own special instruction set so that the instructions can be executed in parallel with low hardware overhead. Our simulations and experiments with a group of benchmarks, largely from Mibench suite, show that on average, 77% performance improvement can be achieved compared to a single pipeline ASIP, with the overheads of 49% on area, 51% on leakage power, 17% on switching activity, and 69% on code size.

Original document

The different versions of the original document can be found in:

• http://www.cse.unsw.edu.au/~sridevan/index_files/07A_4.pdf

• http://www.cse.unsw.edu.au/~sridevan/index_files/07A_4.pdf,

http://www.cecs.uci.edu/~papers/date08/PAPERS/2006/DATE06/PDFFILES/07A_4.PDF,

https://dblp.uni-trier.de/db/conf/date/date2006p.html#RadhakrishnanGP06,

http://yadda.icm.edu.pl/yadda/element/bwmeta1.element.ieee-000001656988,

https://dl.acm.org/citation.cfm?id=1131693,

https://doi.acm.org/10.1145/1131693,

https://academic.microsoft.com/#/detail/2095639094

• http://xplorestaging.ieee.org/ielx5/11014/34699/01656988.pdf?arnumber=1656988,

http://dx.doi.org/10.1109/date.2006.244094