Latest revision as of 00:52, 29 January 2021

Abstract

Soft vector processors (SVPs) achieve significant performance gains through the use of parallel ALUs. However, since ALUs are used in a time-multiplexed fashion, this does not exploit a key strength of FPGA performance: pipeline parallelism. This paper shows how streaming pipelines can be integrated into the datapath of a SVP to achieve dramatic speedups. The SVP plays an important role in supplying the pipeline with high-bandwidth input data and storing its results using on-chip memory. However, the SVP must also perform the housekeeping tasks necessary to keep the pipeline busy. In particular, it orchestrates data movement between on-chip memory and external DRAM, it pre- or post-processes the data using its own ALUs, and it controls the overall sequence of execution. Since the SVP is programmed in C, these tasks are easier to develop and debug than using a traditional HDL approach. Using the N-body problem as a case study, this paper illustrates how custom streaming pipelines are integrated into the SVP datapath and multiple techniques for generating them. Using a custom pipeline, we demonstrate speedups over 7,000 times and performance-per-ALM over 100 times better than Nios II/f. The custom pipeline is also 50 times faster than a naive Intel Core i7 processor implementation.

Original document

The different versions of the original document can be found in:

• http://www.ece.ubc.ca/~lemieux/publications/severance-fpga2014.pdf

• http://www.ece.ubc.ca/~lemieux/publications/severance-fpga2014.pdf,

https://dblp.uni-trier.de/db/conf/fpga/fpga2014.html#SeveranceEOL14,

http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.642.669,

https://dl.acm.org/citation.cfm?id=2554774,

https://academic.microsoft.com/#/detail/1973012690

• http://dl.acm.org/ft_gateway.cfm?id=2554774&ftid=1432288&dwn=1,

http://dx.doi.org/10.1145/2554688.2554774