Latest revision as of 00:12, 29 January 2021

Abstract

With the advent of multi-core architectures, worst case execution time (WCET) analysis has become an increasingly difficult problem. In this paper, we propose a unified WCET analysis framework for multi-core processors featuring both shared cache and shared bus. Compared to other previous works, our work differs by modeling the interaction of shared cache and shared bus with other basic micro-architectural components (e.g. pipeline and branch predictor). In addition, our framework does not assume a timing anomaly free multi-core architecture for computing the WCET. A detailed experiment methodology suggests that we can obtain reasonably tight WCET estimates in a wide range of benchmark programs.

Original document

The different versions of the original document can be found in:

• http://dx.doi.org/10.1109/rtas.2012.26

• http://www.comp.nus.edu.sg/~abhik/pdf/rtas12.pdf

• http://xplorestaging.ieee.org/ielx5/6200017/6200039/06200042.pdf?arnumber=6200042,

http://dx.doi.org/10.1109/rtas.2012.26

• http://yadda.icm.edu.pl/yadda/element/bwmeta1.element.ieee-000006200042,

https://dblp.uni-trier.de/db/conf/rtas/rtas2012.html#ChattopadhyayKRKMF12,

https://ieeexplore.ieee.org/document/6200042,

https://dl.acm.org/citation.cfm?id=2224997,

http://ieeexplore.ieee.org/document/6200042,

https://doi.org/10.1109/RTAS.2012.26,

https://academic.microsoft.com/#/detail/2157297226