Latest revision as of 21:21, 28 January 2021

Abstract

Divide-and-conquer approaches to worst-case execution-time analysis (WCET analysis) pose a safety risk when applied to code for complex modern processors: Interferences between the hardware acceleration mechanisms of these processors lead to timing anomalies, i.e., a local timing change causes an either larger or inverse change of the global timing. This phenomenon may result in dangerous WCET underestimation. This paper presents intermediate results of our work on strategies for eliminating timing anomalies. These strategies are purely based on the modification of software, i.e., they do not require any changes to hardware. In an effort to eliminate the timing anomalies originating from the processor’s out-of-order instruction pipeline, we explored different methods of inserting instructions in the program code that render the dynamic instruction scheduler inoperative. We explain how the proposed strategies remove the timing anomalies caused by the pipeline. In the absence of working solutions for timing analysis for these complex processors, we chose portable metrics from compiler construction to assess the properties of our algorithms.

Original document

The different versions of the original document can be found in:

• http://uhra.herts.ac.uk/bitstream/2299/6268/1/905602.pdf

• http://xplorestaging.ieee.org/ielx5/5479085/5479542/05479566.pdf?arnumber=5479566,

http://dx.doi.org/10.1109/isorc.2010.27

• http://yadda.icm.edu.pl/yadda/element/bwmeta1.element.ieee-000005479566,

http://uhra.herts.ac.uk/bitstream/handle/2299/6268/905602.pdf?sequence=1,

https://uhra.herts.ac.uk/handle/2299/6268,

http://uhra.herts.ac.uk/bitstream/2299/6268/1/905602.pdf,

http://homepages.herts.ac.uk/~rk10aah/papers/rr-2010-p090_isorc10_dependence_insert.pdf,

https://dblp.uni-trier.de/db/conf/isorc/isorc2010.html#KadlecKP10,

https://academic.microsoft.com/#/detail/2108737025