Latest revision as of 18:13, 28 January 2021

Abstract

Domino dynamic circuits are widely used in critical parts of high performance systems. In this paper we show that in addition to the functional limitation associated to the non-inverting behavior of domino gates, there are also performance disadvantages when compared to inverting dynamic gates, which can be related to this feature. These penalties rise from the fact that in order to produce a logic one, a non-inverting gate requires one or more of its inputs to be also at logic one. We analyze the operation of gate-level pipelines implemented with domino and with Delayed Output Evaluation (DOE), an inverting dynamic gate we have recently proposed, and compare their performance. Using domino and DOE gates similar in terms of delay, improvements in operating frequencies around 50% have been obtained by the DOE pipelines.

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Document type: Conference object

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The different versions of the original document can be found in:

• http://hdl.handle.net/10261/155911 under the license https://creativecommons.org/licenses/by-nc-nd

• https://idus.us.es/bitstream/11441/73870/1/DOE%20Based%20High.pdf

• https://idus.us.es/xmlui/handle//11441/73870 under the license cc-by-nc-nd

• http://xplorestaging.ieee.org/ielx7/6942524/6951857/06951902.pdf?arnumber=6951902,

http://dx.doi.org/10.1109/patmos.2014.6951902 under the license http://creativecommons.org/licenses/by-nc-nd/4.0/

• https://digital.csic.es/handle/10261/155911,

https://idus.us.es/handle/11441/73870,

https://dblp.uni-trier.de/db/conf/patmos/patmos2014.html#NunezAQ14,

https://ieeexplore.ieee.org/document/6951902,

https://digital.csic.es/bitstream/10261/155911/1/PATMOS14_IEEE_camera.pdf,

https://academic.microsoft.com/#/detail/2031743178