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Making full use of the capabilities of the FPGA as an accelerator is difficult for non hardware experts, especially if partial reconfiguration is to be employed. One of the issues that arise is to physically implement modules into bounding boxes of minimum size for improving fragmentation cost and reconfiguration time. In this paper we present a method which automates the modules designing step, fulfilling module resource requirements and architectural FPGA constraints. We present a case study that shows how our automatic module implementation flow can be used to generate run-time reconfigurable bitstreams that are suited for stitching together processing pipelines directly from a Maxeler MaxJ HLS specification. This takes into consideration design alternatives, fragmentation, and routing failure mitigation strategies. | Making full use of the capabilities of the FPGA as an accelerator is difficult for non hardware experts, especially if partial reconfiguration is to be employed. One of the issues that arise is to physically implement modules into bounding boxes of minimum size for improving fragmentation cost and reconfiguration time. In this paper we present a method which automates the modules designing step, fulfilling module resource requirements and architectural FPGA constraints. We present a case study that shows how our automatic module implementation flow can be used to generate run-time reconfigurable bitstreams that are suited for stitching together processing pipelines directly from a Maxeler MaxJ HLS specification. This takes into consideration design alternatives, fragmentation, and routing failure mitigation strategies. | ||
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* [https://www.research.manchester.ac.uk/portal/files/64823020/hls_enabled_partially.pdf https://www.research.manchester.ac.uk/portal/files/64823020/hls_enabled_partially.pdf] | * [https://www.research.manchester.ac.uk/portal/files/64823020/hls_enabled_partially.pdf https://www.research.manchester.ac.uk/portal/files/64823020/hls_enabled_partially.pdf] | ||
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| + | * [http://link.springer.com/content/pdf/10.1007/978-3-319-77610-1_20 http://link.springer.com/content/pdf/10.1007/978-3-319-77610-1_20], | ||
| + | : [http://dx.doi.org/10.1007/978-3-319-77610-1_20 http://dx.doi.org/10.1007/978-3-319-77610-1_20] under the license http://www.springer.com/tdm | ||
| + | |||
| + | * [https://link.springer.com/chapter/10.1007/978-3-319-77610-1_20 https://link.springer.com/chapter/10.1007/978-3-319-77610-1_20], | ||
| + | : [https://www.research.manchester.ac.uk/portal/files/64823020/hls_enabled_partially.pdf https://www.research.manchester.ac.uk/portal/files/64823020/hls_enabled_partially.pdf], | ||
| + | : [https://dblp.uni-trier.de/db/conf/arcs/arcs2018.html#GrigoreKK18 https://dblp.uni-trier.de/db/conf/arcs/arcs2018.html#GrigoreKK18], | ||
| + | : [https://www.research.manchester.ac.uk/portal/en/publications/hls-enabled-partially-reconfigurable-module-implementation(83d3aced-2407-4b35-a56a-e199806e1874).html https://www.research.manchester.ac.uk/portal/en/publications/hls-enabled-partially-reconfigurable-module-implementation(83d3aced-2407-4b35-a56a-e199806e1874).html], | ||
| + | : [https://rd.springer.com/chapter/10.1007/978-3-319-77610-1_20 https://rd.springer.com/chapter/10.1007/978-3-319-77610-1_20], | ||
| + | : [https://academic.microsoft.com/#/detail/2786613774 https://academic.microsoft.com/#/detail/2786613774] | ||
| + | |||
| + | * [https://www.research.manchester.ac.uk/portal/en/publications/hls-enabled-partially-reconfigurable-module-implementation(83d3aced-2407-4b35-a56a-e199806e1874).html https://www.research.manchester.ac.uk/portal/en/publications/hls-enabled-partially-reconfigurable-module-implementation(83d3aced-2407-4b35-a56a-e199806e1874).html], | ||
| + | : [https://doi.org/10.1007/978-3-319-77610-1 https://doi.org/10.1007/978-3-319-77610-1], | ||
| + | : [https://pure.manchester.ac.uk/ws/files/64823020/hls_enabled_partially.pdf https://pure.manchester.ac.uk/ws/files/64823020/hls_enabled_partially.pdf] | ||
| − | DOIS: 10.1007/978-3-319-77610- | + | DOIS: 10.1007/978-3-319-77610-1_20 10.1007/978-3-319-77610-1 |
Latest revision as of 15:35, 21 January 2021
Abstract
Making full use of the capabilities of the FPGA as an accelerator is difficult for non hardware experts, especially if partial reconfiguration is to be employed. One of the issues that arise is to physically implement modules into bounding boxes of minimum size for improving fragmentation cost and reconfiguration time. In this paper we present a method which automates the modules designing step, fulfilling module resource requirements and architectural FPGA constraints. We present a case study that shows how our automatic module implementation flow can be used to generate run-time reconfigurable bitstreams that are suited for stitching together processing pipelines directly from a Maxeler MaxJ HLS specification. This takes into consideration design alternatives, fragmentation, and routing failure mitigation strategies.
Original document
The different versions of the original document can be found in:
- http://dx.doi.org/10.1007/978-3-319-77610-1_20 under the license http://www.springer.com/tdm
- http://dx.doi.org/10.1007/978-3-319-77610-1_20 under the license http://www.springer.com/tdm
- https://www.research.manchester.ac.uk/portal/files/64823020/hls_enabled_partially.pdf,
- https://dblp.uni-trier.de/db/conf/arcs/arcs2018.html#GrigoreKK18,
- https://www.research.manchester.ac.uk/portal/en/publications/hls-enabled-partially-reconfigurable-module-implementation(83d3aced-2407-4b35-a56a-e199806e1874).html,
- https://rd.springer.com/chapter/10.1007/978-3-319-77610-1_20,
- https://academic.microsoft.com/#/detail/2786613774
- https://doi.org/10.1007/978-3-319-77610-1,
- https://pure.manchester.ac.uk/ws/files/64823020/hls_enabled_partially.pdf
DOIS: 10.1007/978-3-319-77610-1_20 10.1007/978-3-319-77610-1
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Published on 01/01/2018
Volume 2018, 2018
DOI: 10.1007/978-3-319-77610-1
Licence: CC BY-NC-SA license
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