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Processor simulators are important parts of processor design toolsets in which they are used to verify and evaluate the properties of the designed processors. While simulating architectures with independent function unit pipelines using simulation techniques that avoid the overhead of instruction bit-string interpretation, such as compiled simulation, the simulation of function unit pipelines can become one of the new bottlenecks for simulation speed. This paper evaluates several resource conflict detection models, commonly used in compiler instruction scheduling, in the context of function unit pipeline simulation. The evaluated models include the conventional reservation table based-model, the dynamic collision matrix model, and an finite state automata (FSA) based model. In addition, an improvement to the simulation initialization time by means of lazy initialization of states in the FSA-based approach is proposed. The resulting model is faster to initialize and provides comparable simulation speed to the actively initialized FSA. | Processor simulators are important parts of processor design toolsets in which they are used to verify and evaluate the properties of the designed processors. While simulating architectures with independent function unit pipelines using simulation techniques that avoid the overhead of instruction bit-string interpretation, such as compiled simulation, the simulation of function unit pipelines can become one of the new bottlenecks for simulation speed. This paper evaluates several resource conflict detection models, commonly used in compiler instruction scheduling, in the context of function unit pipeline simulation. The evaluated models include the conventional reservation table based-model, the dynamic collision matrix model, and an finite state automata (FSA) based model. In addition, an improvement to the simulation initialization time by means of lazy initialization of states in the FSA-based approach is proposed. The resulting model is faster to initialize and provides comparable simulation speed to the actively initialized FSA. | ||
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* [http://tce.cs.tut.fi/papers/FU_conflict_detection.pdf http://tce.cs.tut.fi/papers/FU_conflict_detection.pdf] | * [http://tce.cs.tut.fi/papers/FU_conflict_detection.pdf http://tce.cs.tut.fi/papers/FU_conflict_detection.pdf] | ||
| − | * [http://www.springerlink.com/index/pdf/10.1007/978-3-540-73625-7_25 http://www.springerlink.com/index/pdf/10.1007/978-3-540-73625-7_25],[http://dx.doi.org/10.1007/978-3-540-73625-7_25 http://dx.doi.org/10.1007/978-3-540-73625-7_25] | + | * [http://www.springerlink.com/index/pdf/10.1007/978-3-540-73625-7_25 http://www.springerlink.com/index/pdf/10.1007/978-3-540-73625-7_25], |
| + | : [http://dx.doi.org/10.1007/978-3-540-73625-7_25 http://dx.doi.org/10.1007/978-3-540-73625-7_25] | ||
| − | * [https://api.elsevier.com/content/article/PII:S1383762108000593?httpAccept=text/xml https://api.elsevier.com/content/article/PII:S1383762108000593?httpAccept=text/xml],[https://api.elsevier.com/content/article/PII:S1383762108000593?httpAccept=text/plain https://api.elsevier.com/content/article/PII:S1383762108000593?httpAccept=text/plain],[http://dx.doi.org/10.1016/j.sysarc.2008.04.002 http://dx.doi.org/10.1016/j.sysarc.2008.04.002] under the license https://www.elsevier.com/tdm/userlicense/1.0/ | + | * [https://api.elsevier.com/content/article/PII:S1383762108000593?httpAccept=text/xml https://api.elsevier.com/content/article/PII:S1383762108000593?httpAccept=text/xml], |
| + | : [https://api.elsevier.com/content/article/PII:S1383762108000593?httpAccept=text/plain https://api.elsevier.com/content/article/PII:S1383762108000593?httpAccept=text/plain], | ||
| + | : [http://dx.doi.org/10.1016/j.sysarc.2008.04.002 http://dx.doi.org/10.1016/j.sysarc.2008.04.002] under the license https://www.elsevier.com/tdm/userlicense/1.0/ | ||
| − | * [https:// | + | * [https://dblp.uni-trier.de/db/journals/jsa/jsa54.html#JaaskelainenGK08 https://dblp.uni-trier.de/db/journals/jsa/jsa54.html#JaaskelainenGK08], |
| + | : [https://www.sciencedirect.com/science/article/pii/S1383762108000593 https://www.sciencedirect.com/science/article/pii/S1383762108000593], | ||
| + | : [https://doi.org/10.1016/j.sysarc.2008.04.002 https://doi.org/10.1016/j.sysarc.2008.04.002], | ||
| + | : [https://academic.microsoft.com/#/detail/2079377457 https://academic.microsoft.com/#/detail/2079377457] | ||
| − | * [https:// | + | * [https://link.springer.com/chapter/10.1007/978-3-540-73625-7_25 https://link.springer.com/chapter/10.1007/978-3-540-73625-7_25], |
| + | : [https://dblp.uni-trier.de/db/conf/samos/samos2007.html#JaaskelainenGT07 https://dblp.uni-trier.de/db/conf/samos/samos2007.html#JaaskelainenGT07], | ||
| + | : [https://www.scipedia.com/public/Jaaskelainen_et_al_2007a https://www.scipedia.com/public/Jaaskelainen_et_al_2007a], | ||
| + | : [http://tce.cs.tut.fi/papers/FU_conflict_detection.pdf http://tce.cs.tut.fi/papers/FU_conflict_detection.pdf], | ||
| + | : [https://academic.microsoft.com/#/detail/2123220156 https://academic.microsoft.com/#/detail/2123220156] | ||
* [ ] | * [ ] | ||
Latest revision as of 14:36, 21 January 2021
Abstract
Processor simulators are important parts of processor design toolsets in which they are used to verify and evaluate the properties of the designed processors. While simulating architectures with independent function unit pipelines using simulation techniques that avoid the overhead of instruction bit-string interpretation, such as compiled simulation, the simulation of function unit pipelines can become one of the new bottlenecks for simulation speed. This paper evaluates several resource conflict detection models, commonly used in compiler instruction scheduling, in the context of function unit pipeline simulation. The evaluated models include the conventional reservation table based-model, the dynamic collision matrix model, and an finite state automata (FSA) based model. In addition, an improvement to the simulation initialization time by means of lazy initialization of states in the FSA-based approach is proposed. The resulting model is faster to initialize and provides comparable simulation speed to the actively initialized FSA.
Original document
The different versions of the original document can be found in:
- https://api.elsevier.com/content/article/PII:S1383762108000593?httpAccept=text/plain,
- http://dx.doi.org/10.1016/j.sysarc.2008.04.002 under the license https://www.elsevier.com/tdm/userlicense/1.0/
- https://www.sciencedirect.com/science/article/pii/S1383762108000593,
- https://doi.org/10.1016/j.sysarc.2008.04.002,
- https://academic.microsoft.com/#/detail/2079377457
- https://dblp.uni-trier.de/db/conf/samos/samos2007.html#JaaskelainenGT07,
- https://www.scipedia.com/public/Jaaskelainen_et_al_2007a,
- http://tce.cs.tut.fi/papers/FU_conflict_detection.pdf,
- https://academic.microsoft.com/#/detail/2123220156
- [ ]
DOIS: 10.1016/j.sysarc.2008.04.002 10.1007/978-3-540-73625-7_25
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Document information
Published on 01/01/2007
Volume 2007, 2007
DOI: 10.1016/j.sysarc.2008.04.002
Licence: CC BY-NC-SA license
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Keywords
Collision • Compiler • Computer science • Design space exploration • Finite-state machine • Hardware and Architecture • Independent function • Initialization • Instruction schedule • Instruction scheduling • Lazy initialization • Parallel computing • Pipeline transport • Processor design • Real-time computing • Software
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