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Latest revision as of 12:00, 14 October 2020
Abstract
International audience; In a software development lifecycle, it is often more than half of the development time that is dedicated to verification activities. Formal methods offer new possibilities for verification. In the specification phase, simulation or model-checking allow users to detect errors in models. In the implementation phase, analysis techniques, like static analysis, make the verification tasks more exhaustive and more automatic. In this context, we propose to take advantage of these methods to improve embedded software development processes based on the V-model.
Document type: Part of book or chapter of book
Original document
The different versions of the original document can be found in:Document information
Published on 01/01/2012
Volume 2012, 2012
DOI: 10.1007/978-3-642-33609-6_16
Licence: CC BY-NC-SA license
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